The present invention relates to a digital integrated circuit particularly but not exclusively, to a carry look ahead circuit for use in adder circuits.
A parallel arithmetic unit, generally known in the art as a Manchester chain, is disclosed in a Paper No 3302M entitled "A parallel arithmetic unit using a saturated-transistor fast-carry circuit" by T. Kilbuzn, D. B. G. Edwards and D. Aspinall read before the Institute of Electrical Engineers 1st March 1960 and published November 1960 at pages 573 to 584. The Manchester chain is a well known parallel adder in which the addition of two numbers is carried out bit-by-bit in a number of parallel stages. When adding these numbers stage by stage a carry when generated, has to be relayed to the next stage of higher significance and included in the addition operation. A drawback of this type of parallel adder is that it is relatively slow due to the rippling of the carry signal, the signal processing time being proportional to the square of the number of stages. Additionally the carry output from the Manchester chain is non-symmetrical so that if symmetrical carry signals are required, a second, complementary adder is required.
Pages 169 to 171 of "Principles of CMOS VLSI Design - A System Perspective" by N H. E. Weste and K Eshraghian, published by Addison - Wesley publishing Company disclose a cascade voltage switch logic (CVSL). CVSL is a differential style of logic requiring symmetrical signals, that is both true and complement signals, to be routed to gates. In order to be able to produce these signals simultaneously, two complementary NMOS switch structures are provided and connected to a pair of cross-coupled PMOS pull-up transistors. Positive feedback is applied to the PMOS pull-ups to cause the gates to switch.
Modifying CVSL by having cascoded cross-coupled NMOS - PMOS loads instead of the cross-coupled PMOS pull-up transistors, and connecting the gates of the NMOS devices to a reference voltage produces a different electrical behavior which results in much faster switching times. This modified logic having the cascoded cross-coupled NMOS-PMOS loads will be referred to as differential split level (DSL) logic.
Duplicating the switch structures in order to provide true and complement signals has the disadvantage that when integrating the circuits, a relatively large chip area is required for each logic stage because of having to provide dual circuits. If chip area can be saved then this will enable more logic stages to be provided in a chip.